Along with drastically spreading information communication apparatuses and, particularly, personal compact apparatuses, such as mobile devices; memories, logics and other elements composing them are required to have further higher performance, such as higher integration, higher speed and lower power consumption.
Particularly, higher density and a larger capacity of a nonvolatile memory have become more and more significant as a technique of replacing a hard disk basically unable to be more compact due to a movable portion therein and an optical disk.
As a nonvolatile memory, a flash memory using a semiconductor and a FRAM (Ferroelectric Random Access Memory) using ferroelectric substances, etc. may be also mentioned.
However, higher integration of a flash memory is difficult due to the complicated configuration, furthermore, there is a disadvantage that the access time is slow as 100 ns or so. On the other hand, an FRAM is pointed out to have a problem that the number of rewritable times is small.
As high speed nonvolatile memories with a large capacity (highly integrated) and low power consumption but not having the disadvantages as above, a magnetic memory generally called as an MRAM (Magnetic Random Access Memory) memory or MR (Magnetoresistance) memory as described, for example, in the non-patent article 1 has gathered attentions as a result of an improvement of characteristics of a TMR (Tunnel Magnetoresistance) material in recent years.
Moreover, it is expected to an MRAM that higher integration is easy due to the simple configuration, the number of rewritable times is large because recording is performed by rotation of the magnetic moment, and the access time is very high.
A TMR element used in the MRAM gathering attentions in recent years is formed to be configured that a tunnel oxidized film is sandwiched by two magnetic layers and used as a memory element by utilizing the fact that strength of a current flowing in the tunnel oxidized film changes in accordance with the direction of spins of the two magnetic layers.
The MRAM explained above will be explained further in detail. FIG. 1 is a schematic perspective view of a TMR element of an MRAM. The TMR element 10 to be a memory element of a memory cell of the MRAM includes a memory layer 2, wherein the magnetization is rotated relatively easily, and magnetization fixing layers 4 and 6 provided on a support substrate 9. The axis of easy magnetization A1 and the axis of difficult magnetization A2 are as illustrated in the drawing.
The magnetization fixing layer has two magnetization fixing layers: a first magnetization layer 4 and a second magnetization fixing layer 6. Between them is arranged a conductive layer 5, by which the magnetic layers are coupled antiferromagnetically. Nickel, iron, cobalt or ferromagnetic formed by alloys of them are used for the memory layer 2 and the magnetization fixing layers 4 and 6, and ruthenium, copper, chrome, gold and silver, etc. can be used as a material of the conductive layer 5. The second magnetization fixing layer 6 contacts with the antiferromagnetic layer 7, and an exchange interaction between the layers brings the second magnetization fixing layer 6 strong unidirectional magnetic anisotropy. As a material of the antiferromagnetic layer 7, iron, nickel, platinum, iridium, rhodium and other manganese alloy; cobalt and a nickel oxide, etc. may be used. Here, the magnetic fixing layers 4 and 6 and the antiferromagnetic layers 5 and 7 are sometimes included when referring to a pin layer (magnetization fixing layer) 26 (it will be the same below).
Also, between the memory layer 2 as a magnetic layer and the first magnetization fixing layer 4, a tunnel barrier layer 3 formed by an insulator composed of an oxide or nitride, etc. of aluminum, magnesium and silicon, etc. is sandwiched, which cuts magnetic coupling of the memory layer 2 and the magnetization fixing layer 4 and serves for flowing a tunnel current. These magnetic layer and conductive layer are mainly formed by a sputtering method, and the tunnel barrier layer 3 can be obtained by oxidizing or nitriding a metal film formed by sputtering. A topcoat layer 1 serves for preventing mutual dispersion and reducing contact resistance between a TMR element 10 and wiring connected to the TMR element and inhibiting oxidization of the memory layer 2, and a material, such as Cu, Ta and TiN, may be normally used. A base electrode layer 8 is used for connecting a switching element serially connected with the TMR element. The base electrode layer 8 is formed by Ta, etc. and it may also work as the antiferromagnetic layer 7.
In a memory cell configured as above, as will be explained later on, information is read by detecting a change of a tunnel current caused by the magnetic resistance effect and the effect depends on the relative magnetization direction of the memory layer and the magnetization fixing layer.
FIG. 2 is an enlarged simplified perspective view showing a part of a memory cell portion of a general MRAM. Here, while a read circuit portion is omitted for simplification, for example, 9 memory cells are included and bit lines 11 and write word lines 12 intersecting with each other are provided. TMR elements 10 are arranged at these intersections, and writing to the TMR elements 10 is performed by flowing a current to a bit line 11 and a write word line 12 and, by using a synthetic magnetic field of magnetic fields generated thereby, making the magnetization direction of the memory layer 2 of a TMR element 10 at an intersection of the bit line 11 and the write word line 12 to be in parallel or not-parallel to the magnetization fixing layer.
FIG. 3 is a schematic sectional view of a memory cell of an MRAM. For example, an n-type read field-effect transistor 19 composed of a gate insulation film 15 formed on a p-type well region 14 formed in a p-type silicon semiconductor substrate 13, a gate electrode 16, a source region 17 and a drain region 18 is arranged and, above thereof, a write word line 12, a TMR element 10 and a bit line 11 are arranged. A source region 17 is connected to a sense line 21 via a source electrode 20. The field-effect transistor 19 functions as a switching element for reading, and read wiring 22 drawn from between the word line 12 and the TMR element 10 is connected to a drain region 18 via a drain electrode 23. Note that the transistor 19 may be an n-type or p-type field-effect transistor and, other than that, a diode, bipolar transistor, MESFET (Metal Semiconductor Field Effect Transistor) and other variety of switching elements may be used.
FIG. 4 is an equivalent circuit diagram of an MRAM. A portion including, for example, 6 memory cells is shown. Mutually intersecting bit lines 11 and write word lines 12 are provided, and intersections of the writing lines are provided with a memory element 10, a field-effect transistor 19 connected to the memory element 10 and for selecting an element at the time of reading, and a sense line 21. The sense line 21 is connected to a sense amplifier 23 and detects stored information. Note that the reference number 24 in the figure indicates bidirectional write word line current drive circuit, and the reference number 25 indicates a bit line current drive circuit.
FIG. 5 is a magnetic field response characteristic diagram (asteroid curve) at the time of writing to an MRAM. Inverted thresholds in the memory layer magnetization direction caused by applied magnetic field HEA in the axis direction of easy magnetization and magnetic field HHA in the axis direction of difficult magnetization are shown. When an equivalent synthetic magnetic field vector is generated outside of the asteroid curve, magnetic field inversion arises, while, synthetic magnetic field vectors inside the asteroid curve do not invert the cell from one side in the current bistable state. Also, cells at other intersections than that of the current flowing word line and bit line are applied with a magnetic field generated by a word line or bit line alone. Therefore, when the size is larger than the unidirectional inverted magnetic field HK, a magnetization direction of the cells at other intersections are also inverted, so that it is set that writing to the selected cell becomes possible only when the synthetic magnetic field is in a gray region in the figure.
As explained above, in the MRAM, it is general that the asteroid magnetization inversion characteristics are utilized by using two writing lines, that is, a bit line and a word line to selectively write only to a specified memory cell due to the inversion of magnetization spins. Synthetic magnetization in a single memory region is determined by vector synthesis of a magnetic field HEA in the axis direction of easy magnetization and a magnetic field HHA in the axis direction of difficult magnetization applied to that. A writing current flowing in the bit lines applies a magnetic field HEA in the axis direction of easy magnetization to cells, while a current flowing in the word lines applies a magnetic field HHA in the axis direction of difficult magnetization to the cells.
FIG. 6 is a schematic view for explaining a reading operation principle of an MRAM. Here, the layer configuration of the TMR element 10 is schematically illustrated, wherein the pin layer explained above is indicated as a single layer pin layer 26 and illustration of other portions than the memory layer 2 and the tunnel barrier layer 3 is omitted.
Namely, as explained above, in writing of information, magnetization spins MS of the cells are inverted by synthetic magnetic field at intersections of the bit lines 11 and word lines 12 wired in matrix and the directions are recorded as information of “1” and “0”. Also, reading is performed by using a TMR effect applied from the magnetic resistance effect. The TMR effect is a phenomena that the resistance value changes in accordance with the direction of the magnetization spins MS, and “1” and “0” of information are detected based on a state where the magnetization spins MS has high not-parallel resistance and a state where the magnetization spins MS has low parallel resistance. The reading is performed by flowing of a reading current (tunnel current) I between the word lines 12 and bit lines 11 and reading outputs in accordance with high and low levels of the resistance as explained above to the sense line 21 through the read field-effect transistor 19 as explained above.
Main steps of a production method of an MRAM having the above conventional configuration will be explained with reference to FIG. 7A and FIG. 7B.
As shown in FIG. 7A, on an interlayer insulation film composed of a silicon oxide film formed on a substrate (not shown), on which a Tr (transistor) and a wiring layer are formed by using a CMOS technique; word lines 12 and read line 123 are formed as buried wiring in a memory portion A, and lower layer wiring 33 and 34 as buried wiring are formed in a peripheral circuit portion B.
A diffusion prevention film 32 formed by a silicon nitride film for preventing diffusion of copper ions of the wiring is formed on the word lines and the lower layer wiring 33 and 34 in the peripheral circuit portion B. After furthermore stacking an interlayer insulation film 35 composed of a silicon oxide film 35, wiring connection portions 123a are formed in contact holes 100 formed by opening by etching the interlayer insulation film 35 on the reading lines 123. On top of that, respective component layers of, for example, a pin layer 26 including Ta/PtMn/CoFe (a second pin layer)/Ru/CoFe (a first pin layer), a tunnel barrier layer 3 formed by AlO3, a free layer 2 formed by CoFe-30B, and a topcoat layer 1 formed by TiN are stacked.
Then, to form a TMR element 10, by using a mask 101 composed of a stacked film of SiO/SiN formed to be a predetermined pattern, the topcoat layer 1 and the free layer 2 are etched above the word lines 12 to have a predetermined pattern and, furthermore, the whole surface is covered with an insulation film 102 of SiO2, etc.
Note that, to form the buried wiring, it is sufficient if a copper diffusion barrier film formed, for example, by Ta is provided to wiring grooves, the Damascene method, etc. using the barrier film as a seed metal is performed to apply Cu by electrolytic plating, then, CMP (chemical mechanical polishing processing) is performed (it will be the same in other wiring below).
Next, as shown in FIG. 7B, by using other photoresist or a mask 103 composed of a stacked film of SiO/SiN having a predetermined pattern, the insulation film 102, tunnel barrier layer 3 and pin layer 26 are subjected to stacking etching to form the same pattern to separate between adjacent TMR elements 10 and to connect the respective TMR elements to the reading line 123 (123a) via the pin layer 26. At this time, the interlayer insulation film 35 is also partially etched.
Next, while the illustration is omitted, an interlayer insulation film and a diffusion prevention film are stacked, after forming contact holes (not shown) thereon, the contact holes are buried by Cu plating, then, bit lines are formed on the TMR elements 10 in the memory portion A and bit lines are connected to the lower wiring in the peripheral circuit portion B.
When producing an MRAM as explained above, in the element separation step in FIG. 7B, a method of performing etching on the tunnel barrier layer 3 to the pin layer 26 by ion milling using Ar ions may be considered so far (refer to the patent articles 1 and 2).
Patent Article 1: the Japanese Unexamined Patent Publication No. 2003-60169 (line 21 on right column on page 3 to line 8 on left column on page 4, FIG. 1(2) to (5))
Patent Article 2: the Japanese Unexamined Patent Publication No. 2003-31772 (lines 24 to 34 on left column on page 5, FIG. 1(3))
Non-patent Article 1: Wang et al. IEEE Trans. Magn. 33 (1997), 4498